Circular imports bug

[ellial]

Hello,

I have been trying to run this framework using :
python3 auto_create_verilog.py --prompt="./verilogeval_prompts_tbs/validation_set/circuit4/circuit4.sv" --name="top_module1" --testbench="./verilogeval_prompts_tbs/validation_set/circuit4/circuit4_tb.sv" --outdir="sol.txt" --log="log.txt" --model-family=ChatGPT --model-id=gpt-4o

However, I get a circular import error due to some import dependency
File "/AutoChip/autochip_scripts/auto_create_verilog.py", line 3, in <module> import languagemodels as lm File "/AutoChip/autochip_scripts/languagemodels.py", line 28, in <module> import verilog_handling as vh File "/AutoChip/autochip_scripts/verilog_handling.py", line 13, in <module> def compile_iverilog(outdir,module,compiler_cmd,response:lm.LLMResponse): AttributeError: partially initialized module 'languagemodels' has no attribute 'LLMResponse' (most likely due to a circular import)

Is there a way around this error without having to restructure the code/imports?

[JBlocklove]

Sorry it took a bit to get back to this! It looks like there had been a bit of a mismatch between the documentation and the current state of the code. auto_create_verilog.py is no longer the main script to be called (I just removed it to avoid any of this confusion in the future).

It looks like some of your paths and names also aren't quite the same as what we have by default in the repo. I just freshly cloned the repo and I was able to run what you were trying with this command (run from autochip_scripts):

python generate_verilog.py --prompt="../verilogeval_prompts_tbs/validation_set/circuit4/circuit4.sv" --name="top_module" --testbench="../verilogeval_prompts_tbs/validation_set/circuit4/circuit4_tb.sv" --outdir="sol.txt" --log="log.txt" --model-family=ChatGPT --model-id=gpt-4o

You could also use our newer configuration file setup, which IMO is a cleaner way to work with AutoChip. Your file would look like this:

{
	"general": {
        "prompt": "../verilogeval_prompts_tbs/validation_set/circuit4/circuit4.sv",
        "name": "top_module",
        "testbench": "./verilogeval_prompts_tbs/validation_set/circuit4/circuit4_tb.sv",
	"model_family": "ChatGPT",
	"model_id": "gpt-4o-mini",
	"num_candidates": 1,
	"iterations": 10,
        "outdir": "sol.txt",
        "log": "log.txt",
	"mixed-models": false
    }
}