All pull requests

Pull requests

• [Feature] Add native ConvRot INT8 kernels for Intel BMG GPUs

  #589·YangKai0616 opened Oct 29, 2026Collaborator·

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  4

• [MoE] Locate each tile's expert in parallel for decode-sized grouped GEMMs

  #588·AgainstEntropy opened Oct 27, 2026·

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  2

• [GEMM] Add Xe2 dense FP8 W8A16 GEMM with in-work-group split-K

  #587·AgainstEntropy opened Oct 27, 2026·

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  4

• [QKNORM] optimize qknorm with warp launch and vector select

  #585·MeowMiaoJ opened Oct 27, 2026Contributor·

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  6

• [MOE]Avoid device copy of problem size in mxfp4 group gemm

  run-ci
  #584·gaopengff opened Oct 27, 2026Collaborator·

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  3

• [FMHA] Support seqused_q / seqused_k in non-paged varlen prefill

  #583·desmond-intel opened Oct 26, 2026Contributor·

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  9

• [Feat] Add bit-exact eager-rounding mode to fused_inplace_qknorm_rope

  #582·mehersai07 opened Oct 26, 2026·

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  1

• [CI] [Intel] ci/xpu: Add a CRI (Xe3P) build gate to PR CI

  run-ci
  #580·arathi-hlab opened Oct 26, 2026Collaborator·3 tasks done·

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• [ADD] head_dim 96 support on fusead_qk_norm_rope

  #579·MeowMiaoJ opened Oct 26, 2026Contributor·

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• [Feat] Add HC ops for Qwen3.8-flash-next

  run-ci
  #578·Xia-Weiwen opened Oct 26, 2026Collaborator·4/4·

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  23

• [BMG] moe_grouped_mm_nt_xe20: allow n_experts not a multiple of 8

  run-ci
  #577·Maheswarareddy-ctrl opened Oct 26, 2026·

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  3

• [FMHA] Add optional ALiBi slopes to the paged FMHA kernels

  run-ci
  #573·desmond-intel opened Oct 23, 2026Contributor·

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  14

• Implement mxfp4 indexer using sycl

  run-ci
  #572·cyxlily opened Oct 22, 2026Collaborator·

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  39

• [Perf] gemm: Extend BF16 prefill to validated intermediate rows

  #561·alexnails opened Oct 18, 2026Collaborator·

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• Add packed INT4 GPTQ decode and page sizes 64 and 128

  #560·krisclarkdev opened Oct 17, 2026·4 tasks done·

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• [Perf] gemm: Reuse BF16 prefill GEMM for narrow gate/up

  #559·alexnails opened Oct 17, 2026Collaborator·

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• [Perf] gemm: Accelerate wide BF16 gate/up prefill on Xe20

  #558·alexnails opened Oct 17, 2026Collaborator·

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• [Perf] Fuse Xe2 BF16 gate/up GEMM with an exact GELU lookup epilogue

  #557·alexnails opened Oct 17, 2026Collaborator·

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• [Perf] Add Xe2 BF16 vocabulary GEMM with compact rank argmax

  #556·alexnails opened Oct 17, 2026Collaborator·

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• [Intel] Add Xe2 BF16 dense GEMM with static scheduling and register pipelining

  #555·alexnails opened Oct 17, 2026Collaborator·

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• Decode LoRA kernels are optimized

  run-ci
  #550·srujan-thomdapu opened Oct 15, 2026Collaborator·

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  19

  

• Add Minimax-H3 related kernels

  #545·MeowMiaoJ opened Oct 14, 2026Contributor·

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  5

• [Norm] Support a strided last dim in gemma_rmsnorm

  #544·desmond-intel opened Oct 14, 2026Contributor·

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  1

• Upstream more unit test configurations

  run-ci
  #542·mkumargarg opened Oct 13, 2026Collaborator·

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  7

• [XPU] SYCL port of the ngram-embedding kernels (LongCat-Flash)

  #532·desmond-intel opened Oct 9, 2026Contributor·

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  5