phsauter · Sep 3, 2026 · Jul 30, 2026 · Jul 30, 2026 · Aug 11, 2026 · Aug 11, 2026
diff --git a/Bender.yml b/Bender.yml
@@ -51,3 +51,7 @@ sources:
   - target: dm_mem_test
     files:
     - tb/dm_mem/tb_dm_mem.sv
+
+  - target: multihart_resume_test
+    files:
+    - tb/dm_top/tb_dm_top_multihart_resume.sv
diff --git a/CHANGELOG.md b/CHANGELOG.md
@@ -6,6 +6,14 @@ and this project adheres to [Semantic Versioning](http://semver.org/spec/v2.0.0.
 
 ## Unreleased
 
+### Fixed
+- Keep accepted resume requests pending per hart until acknowledged, clear resumeack only for the
+  request target, and retain resumeack across ndmreset; widen the internal dm_csrs/dm_mem
+  clear_resumeack connection from scalar to a per-hart vector and add a dmactive reset input to
+  dm_mem for resumeack state.
+- Reject out-of-range hart IDs reported through debug memory before updating per-hart state.
+- Make the write-only `dmcontrol.haltreq` field read as zero (#161).
+
 ## [0.10.1] - 2026-08-07
 ### Changed
 - Replace the obsolete Travis CI infrastructure with public GitHub Actions checks for licenses,

diff --git a/ci/Makefile b/ci/Makefile
@@ -7,13 +7,27 @@
 
 ROOT := $(abspath $(dir $(lastword $(MAKEFILE_LIST)))/..)
 TB := $(ROOT)/tb
+VERILATOR_FILE_LIST := $(ROOT)/build/verilator/sources.flist
 
 NUM_JOBS ?= 2
 OPENOCD_PREFIX ?= $(ROOT)/.cache/openocd
 
-.PHONY: all compliance dm-mem firmware full-model jtag-dmi openocd
+.PHONY: all compliance dm-mem firmware full-model jtag-dmi multihart-resume openocd \
+	verilator-sources
 
-all: dm-mem jtag-dmi compliance
+all: dm-mem jtag-dmi multihart-resume compliance
+
+verilator-sources:
+	cd $(ROOT) && bender checkout
+	mkdir -p $(dir $(VERILATOR_FILE_LIST))
+	cd $(ROOT) && bender script flist-plus \
+		--relative-path \
+		-t riscv-dbg:simulation \
+		-t riscv-dbg:test \
+		-t riscv-dbg:dm_mem_test \
+		-t riscv-dbg:multihart_resume_test \
+		-t tech_cells_generic:tech_cells_generic_exclude_deprecated \
+		> $(VERILATOR_FILE_LIST)
 
 full-model:
 	$(MAKE) -C $(TB) -j1 download_deps
@@ -26,14 +40,18 @@ openocd:
 	NUM_JOBS=$(NUM_JOBS) OPENOCD_PREFIX=$(OPENOCD_PREFIX) \
 		$(ROOT)/ci/get-openocd.sh
 
-jtag-dmi:
+jtag-dmi: verilator-sources
 	JTAG_BUILD_DIR=$(ROOT)/build/jtag-verilator \
 		$(ROOT)/ci/run-jtag-verilator.sh
 
-dm-mem:
+dm-mem: verilator-sources
 	DM_MEM_BUILD_DIR=$(ROOT)/build/dm-mem-verilator \
 		$(ROOT)/ci/run-dm-mem-verilator.sh
 
+multihart-resume: verilator-sources
+	MULTIHART_BUILD_DIR=$(ROOT)/build/multihart-verilator \
+		$(ROOT)/ci/run-multihart-verilator.sh
+
 compliance: full-model firmware openocd
 	cd $(TB) && \
 		OPENOCD=$(OPENOCD_PREFIX)/bin/openocd \

diff --git a/ci/run-dm-mem-verilator.sh b/ci/run-dm-mem-verilator.sh
@@ -10,7 +10,6 @@ set -euo pipefail
 
 readonly ROOT="$(cd "$(dirname "${BASH_SOURCE[0]}")/.." && pwd)"
 readonly BUILD_DIR="${DM_MEM_BUILD_DIR:-${ROOT}/build/dm-mem-verilator}"
-readonly FILE_LIST="${BUILD_DIR}/sources.flist"
 
 # Fields: name BusWidth MaxRegisterAccessWidth HartSel AarSize ExpectSupported
 readonly TEST_CASES=(
@@ -23,34 +22,13 @@ readonly TEST_CASES=(
   "bus64_max64_aar64 64 64 1 3 1"
 )
 
-mkdir -p "${BUILD_DIR}"
-cd "${ROOT}"
-
-bender checkout
-bender script flist-plus \
-  --relative-path \
-  -t riscv-dbg:dm_mem_test \
-  -t tech_cells_generic:tech_cells_generic_exclude_deprecated \
-  > "${FILE_LIST}"
-
 for test_case in "${TEST_CASES[@]}"; do
   read -r name bus_width max_access_width hart_sel aar_size expect_supported <<< "${test_case}"
-  case_build_dir="${BUILD_DIR}/${name}"
-  mkdir -p "${case_build_dir}"
-
-  verilator \
-    --binary \
-    --timing \
-    -Wno-fatal \
-    -DCOMMON_CELLS_ASSERTS_OFF \
-    --top-module tb_dm_mem \
-    --Mdir "${case_build_dir}/obj_dir" \
+  "${ROOT}/ci/run-single-top-verilator.sh" \
+    "${BUILD_DIR}/${name}" tb_dm_mem \
     -GBusWidth="${bus_width}" \
     -GMaxRegisterAccessWidth="${max_access_width}" \
     -GHartSel="${hart_sel}" \
     -GAarSize="${aar_size}" \
-    -GExpectSupported="${expect_supported}" \
-    -f "${FILE_LIST}"
-
-  "${case_build_dir}/obj_dir/Vtb_dm_mem"
+    -GExpectSupported="${expect_supported}"
 done
diff --git a/ci/run-jtag-verilator.sh b/ci/run-jtag-verilator.sh
@@ -10,26 +10,7 @@ set -euo pipefail
 
 readonly ROOT="$(cd "$(dirname "${BASH_SOURCE[0]}")/.." && pwd)"
 readonly BUILD_DIR="${JTAG_BUILD_DIR:-${ROOT}/build/jtag-verilator}"
-readonly FILE_LIST="${BUILD_DIR}/sources.flist"
 
-mkdir -p "${BUILD_DIR}"
-cd "${ROOT}"
-
-bender checkout
-bender script flist-plus \
-  --relative-path \
-  -t riscv-dbg:simulation \
-  -t riscv-dbg:test \
-  -t tech_cells_generic:tech_cells_generic_exclude_deprecated \
-  > "${FILE_LIST}"
-
-verilator \
-  --binary \
-  --timing \
-  -Wno-fatal \
-  -DCOMMON_CELLS_ASSERTS_OFF \
-  --top-module tb_jtag_dmi \
-  --Mdir "${BUILD_DIR}/obj_dir" \
-  -f "${FILE_LIST}"
-
-"${BUILD_DIR}/obj_dir/Vtb_jtag_dmi"
+exec "${ROOT}/ci/run-single-top-verilator.sh" \
+  "${BUILD_DIR}" \
+  tb_jtag_dmi
diff --git a/ci/run-multihart-verilator.sh b/ci/run-multihart-verilator.sh
@@ -0,0 +1,32 @@
+#!/usr/bin/env bash
+# Copyright 2026 ETH Zurich and University of Bologna.
+# Solderpad Hardware License, Version 0.51, see LICENSE for details.
+# SPDX-License-Identifier: SHL-0.51
+#
+# Authors:
+# - Philippe Sauter <phsauter@iis.ee.ethz.ch>
+
+set -euo pipefail
+
+readonly ROOT="$(cd "$(dirname "${BASH_SOURCE[0]}")/.." && pwd)"
+readonly BUILD_DIR="${MULTIHART_BUILD_DIR:-${ROOT}/build/multihart-verilator}"
+
+"${ROOT}/ci/run-single-top-verilator.sh" \
+  "${BUILD_DIR}/three-hart" tb_dm_top_multihart_resume \
+  -GNrHarts=3 -GSelectableHarts="3'b101"
+
+"${ROOT}/ci/run-single-top-verilator.sh" \
+  "${BUILD_DIR}/singleton" tb_dm_top_multihart_resume \
+  -GNrHarts=1 -GSelectableHarts="1'b1"
+
+"${ROOT}/ci/run-single-top-verilator.sh" \
+  "${BUILD_DIR}/four-hart" tb_dm_top_multihart_resume \
+  -GNrHarts=4 -GSelectableHarts="4'b1111"
+
+"${ROOT}/ci/run-single-top-verilator.sh" \
+  "${BUILD_DIR}/five-hart" tb_dm_top_multihart_resume \
+  -GNrHarts=5 -GBusWidth=32 -GSelectableHarts="5'b11111"
+
+"${ROOT}/ci/run-single-top-verilator.sh" \
+  "${BUILD_DIR}/nine-hart" tb_dm_top_multihart_resume \
+  -GNrHarts=9 -GBusWidth=64 -GSelectableHarts="9'b111111111"
diff --git a/ci/run-single-top-verilator.sh b/ci/run-single-top-verilator.sh
@@ -0,0 +1,41 @@
+#!/usr/bin/env bash
+# Copyright 2026 ETH Zurich and University of Bologna.
+# Solderpad Hardware License, Version 0.51, see LICENSE for details.
+# SPDX-License-Identifier: SHL-0.51
+#
+# Authors:
+# - Philippe Sauter <phsauter@iis.ee.ethz.ch>
+
+set -euo pipefail
+
+if (($# < 2)); then
+  echo "usage: $0 BUILD_DIR TOP_MODULE [VERILATOR_ARG ...]" >&2
+  exit 2
+fi
+
+readonly ROOT="$(cd "$(dirname "${BASH_SOURCE[0]}")/.." && pwd)"
+readonly BUILD_DIR="$(realpath -m -- "$1")"
+readonly TOP_MODULE="$2"
+shift 2
+readonly FILE_LIST="${ROOT}/build/verilator/sources.flist"
+
+if [[ ! -f "${FILE_LIST}" ]]; then
+  echo "error: Verilator file list not found: ${FILE_LIST}" >&2
+  echo "run 'make -C ci verilator-sources' first" >&2
+  exit 2
+fi
+
+mkdir -p "${BUILD_DIR}"
+cd "${ROOT}"
+
+verilator \
+  --binary \
+  --timing \
+  -Wno-fatal \
+  -DCOMMON_CELLS_ASSERTS_OFF \
+  --top-module "${TOP_MODULE}" \
+  --Mdir "${BUILD_DIR}/obj_dir" \
+  "$@" \
+  -f "${FILE_LIST}"
+
+"${BUILD_DIR}/obj_dir/V${TOP_MODULE}"
diff --git a/doc/debug-system.md b/doc/debug-system.md
@@ -88,7 +88,7 @@ Accessing a non-implemented register will return `0`.
 
 **Field**       | **Access** | **(Reset) Value** | **Comment**
 --------------- | ---------- | ----------------- | -------------------------------------------------------------------------------------------------------------
-haltreq         | WARZ
+haltreq         | W
 resumereq       | W1
 hartreset       | WARL       | 0                 | Not implemented, reads constant 0
 ackhavereset    | W1