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Fixes openhwfoundation#3588. aes32esi/esmi/dsi/dsmi, sha512sig0h/0l/1h/1l and sha512sum0r/1r are defined for RV32 only, and on RV64 the instr[31:20] = 12'b011010011000 encoding is not rev8 (the RV64 rev8 is 12'b011010111000). core/decoder.sv matched all of them on CVA6Cfg.ZKN alone, so on RV64 they decoded to real operations and retired instead of raising illegal-instruction (the vendored Spike raises mcause=2). Add the CVA6Cfg.IS_XLEN32 term, as openhwfoundation#3527 did for zip/unzip. The new test decoder-zkn-rv32-only-rv64 checks that each of the eleven encodings traps with mcause=2 on RV64 and that the RV64 forms (aes64es, aes64esm, sha512sum0, sha512sig0, rev8) still retire.
The converse of the previous change. aes64es/esm/ds/dsm/ks2, aes64ks1i, aes64im, sha512sig0/1 and sha512sum0/1 are defined for RV64 only, but core/decoder.sv matched them on CVA6Cfg.ZKN alone, and cv32a6_imac_sv32 enables ZKN: on that configuration aes64es retires instead of raising illegal-instruction. Add the CVA6Cfg.IS_XLEN64 term. The new test decoder-zkn-rv64-only-rv32 checks that each of the eleven encodings traps with mcause=2 on RV32 and that the RV32 forms (aes32esi, sha512sum0r, sha256sum0, rev8) still retire.
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Fixes #3588.
core/decoder.svmatches several Zkn encodings onCVA6Cfg.ZKNalone, with no XLEN term. On the XLEN where these instructions do not exist, they decode as real operations and retire instead of raising illegal-instruction:cv64a6_imafdc_sv39): the RV32-onlyaes32esi/esmi/dsi/dsmi,sha512sig0h/0l/1h/1landsha512sum0r/1r, and the RV32 encoding ofrev8(instr[31:20] == 12'b011010011000). This is what [BUG] <RV32-only Zkn instructions (aes32*,sha512*h/l/r) and the RV32rev8encoding still retire on RV64 after #3527> #3588 reports.cv32a6_imac_sv32, which enables ZKN): the RV64-onlyaes64es/esm/ds/dsm/ks2,aes64ks1i,aes64im,sha512sig0/1andsha512sum0/1. [BUG] <RV32-only Zkn instructions (aes32*,sha512*h/l/r) and the RV32rev8encoding still retire on RV64 after #3527> #3588 mentions this direction as untested;aes64esdoes retire on that configuration.The vendored Spike raises illegal-instruction (
mcause=2) for all of them.This PR follows #3527, which fixed
zip/unzipthe same way:CVA6Cfg.IS_XLEN32to the RV32-only matches.CVA6Cfg.IS_XLEN64to the RV64-only matches.Only
core/decoder.svchanges.Tests
Two directed tests are added in
verif/tests/custom/issues/and registered intestlist_issues.yaml. Each checks that eleven encodings trap withmcause=2and that the valid forms on that XLEN still retire.decoder-zkn-rv32-only-rv64cv64a6_imafdc_sv39tohost = 1:aes32esiretires)decoder-zkn-rv64-only-rv32cv32a6_imac_sv32tohost = 1:aes64esretires)Both tests also pass on the vendored Spike, with 11 illegal-instruction traps each. The testharnesses were built with Verilator 5.008 and run with
--iss=veri-testharness.As a regression check, the same programs were run on the baseline and patched
cv64a6_imafdc_sv39testharnesses, and each trace was compared against Spike. The verdicts are identical for 331 floating-point programs and 96 interrupt programs; a batch of trigger programs is still running. The full CI regression has not been run.The second commit goes beyond the issue as filed. I am happy to move it to a separate PR if you prefer.