Realtek RTL8127 10GbE PCIe

This repository contains the source code provided by Realtek for the RTL8127 10GbE PCIe controllers.

The source code is provided by Realtek as-is, without any kind of changelog. Git is only used for tracking down the changes introduced between versions.

Original sources

You can find the original files provided by Realtek here.

The same files from Realtek are provided as release assets.

Disclaimer

Bug reports or issues should be reported directly to Realtek.

This repository is used for OpenWrt development because the files provided by Realtek are protected with CAPTCHAs and can't be used for creating OpenWrt packages.

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Local patches

The following patches are applied on top of the upstream Realtek source to fix PTP hardware timestamping on the RTL8127A. They were developed and validated on a Qualcomm DragonWing IQ-9075 running Linux 6.18.12 (aarch64).

Patch 1 — arm PTP capture engine correctly at probe time (62ba467)

Files: r8127.h, r8127_n.c, r8127_ptp.c, r8127_ptp.h

Problem

Hardware timestamping produced zero timestamps on every TX and RX packet despite ptp4l successfully writing PTP_CTL = 0x103F via SIOCSHWTSTAMP. PTP_INSR read back 0x0000 at every TX timeout, confirming the PHY capture pipeline was never generating timestamp-ready interrupts.

The upstream driver wrote register 0xA640 BIT_15 (the PHY timestamp capture engine arm bit) from within rtl8127_ptp_enable_config(), which is called from the hwtstamp_enable(true) path that ptp4l triggers via SIOCSHWTSTAMP. This caused two separate bugs:

1. Infinite link-drop loop. Writing 0xA640 BIT_15 triggers a PHY autoneg restart, which drops the link. ptp4l monitors the link and calls SIOCSHWTSTAMP again on each link-up event, which writes 0xA640 again, which drops the link again — repeating indefinitely.

2. Capture engine never armed. The PHY only activates its internal timestamp pipeline when 0xA640 BIT_15 is written while PTP_CTL is already non-zero. When the link-drop loop was broken by removing 0xA640 from the enable path and moving it to the probe-time rtl8127_ptp_reset(), the probe code called hwtstamp_enable(false) first (leaving PTP_CTL = 0x0000), then wrote 0xA640. The register write was accepted but the pipeline never activated (PTP_INSR remained 0x0000).

Fix

rtl8127_ptp_reset() (called once at probe / hardware reset) now:

1. Calls hwtstamp_enable(false) to reach a clean state.
2. Calls rtl8127_ptp_enable_config() under phy_lock to set PTP_CTL = 0x103F.
3. Writes 0xA640 BIT_15 while PTP_CTL is non-zero — the PHY arms the capture pipeline and then triggers an autoneg restart that resets all OCP registers (including PTP_CTL) back to zero.
4. Sets RTL_FLAG_PTP_ENGINE_ARMED so hwtstamp_enable() never writes 0xA640 again after the engine has been primed.

When ptp4l calls SIOCSHWTSTAMP after the link comes back up, hwtstamp_enable(true) re-writes PTP_CTL = 0x103F. Because the capture pipeline was already armed during probe, PTP_INSR now correctly signals TX_TX_INTR on every egress PTP packet.

Additional changes in this patch

Change	Reason
hwtstamp_enable(disable) writes PTP_CTL = 0x0000 instead of clearing BIT_0 only	Clearing only BIT_0 leaves the PHY in a partial PTP mode that causes the link partner to timeout and drop the link
New rtl8127_ptp_link_up_init(), called from rtl8127_link_on_patch	Re-writes PTP_CTL and PTP_INER after any link recovery while hwtstamp is enabled; the upstream code only called rtl8127_set_local_time() on link-up, which did not restore the PTP capture configuration
hrtimer_init() + manual .function assignment → hrtimer_setup()	hrtimer_setup() is the preferred API from kernel 6.15 onward
Debug logging: INSR/TRX_STA/PTP_CTL readbacks on TX timeout and ingress path; all PTP log messages rate-limited with net_ratelimit()	Aids diagnosis; netdev_warn_ratelimited() / netdev_info_ratelimited() are not present in all 6.x kernel builds

Critical constraints

• 0xA640 BIT_15 must only be written at module probe or hardware reset — never from hwtstamp_enable(). Writing it while a link partner is connected drops the link. If the write is repeated (e.g. from a link-up → SIOCSHWTSTAMP loop) the switch port can accumulate flap state and stay down for 120+ seconds.
• PTP_CTL must be non-zero when 0xA640 BIT_15 is written — otherwise the PHY timestamp capture pipeline does not activate.

Testing

Validated on Qualcomm DragonWing IQ-9075, RTL8127A, kernel 6.18.12-aarch64:

ptp4l -i enP1p1s0 --step_threshold 1.0 --tx_timestamp_timeout 100 -m

• ptp4l transitions to MASTER and holds the role without TX timestamp timeouts.
• dmesg shows PTP: TX_TX_INTR seen on every Sync/Announce egress (~1 Hz).
• No link drops after SIOCSHWTSTAMP; PTP_CTL readback = 0x103f confirmed.