Add Catalyst N1 & N2 neuromorphic processors to hardware guide

[Mr-wabbit]

Summary

This PR adds a new hardware entry for the Catalyst N1 and N2 neuromorphic processors to the hardware guide.

Catalyst N1 and N2 are open-architecture digital neuromorphic processors deployed on Xilinx VU47P FPGAs (AWS F2 instances), designed by Catalyst Neuromorphic Ltd. Key specifications:

• 128 neurosynaptic cores, 131,072 CUBA LIF neurons, 134M max synapses (CSR sparse encoding)
• On-chip learning: STDP, three-factor learning rules, per-group plasticity
• N1: Full Intel Loihi 1 feature parity
• N2: Full Loihi 2 feature parity — programmable neuron microcode, 5 neuron models (CUBA, Izhikevich, adLIF, Sigma-Delta, R&F), graded spikes, convolutional synapses
• Published benchmarks: SHD 90.7%, N-MNIST 99.2%, SSC 72.1%, Google Speech Commands 88.0%
• Published papers: N1 (Zenodo), N2 (Zenodo)
• Cloud API available at api.catalyst-neuromorphic.com

The entry follows the neuromorphic-hardware archetype format and includes all required front matter fields.

Checklist

• Follows neuromorphic-hardware archetype structure
• Front matter includes all product specification fields
• Includes overview, architecture, software, benchmarks, publications, and availability sections
• Org logo image included
• Higher-resolution product/chip image (can provide if requested)

Notes

The main image currently uses the GitHub org avatar. I'm happy to provide a higher-resolution hardware diagram or chip image if the maintainers prefer a different visual.

[neural-loop]

Hi @eljoserass Could you review this please?

[aMarcireau]

This looks very interesting and I think that this has its place on the ONM website.

However, our hardware category only lists ASICs for now. Catalysts' N1 and N2 architectures are almost software-like in my opinion (I am tempted to compare them to GPU compute shaders, except that they target cloud FPGAs) and might be a better fit for our software list (or perhaps in a brand-new "FPGA" category?).

As a side note, were the articles listed in "published papers" peer-reviewed and published in scientific journals, or are they white papers from the company? Could you precise your role or relationship with the company Catalyst and the University of Aberdeen?

[Mr-wabbit]

Thanks for the review, and fair point on all three.

On categorization: Catalyst is RTL (Verilog), not a software simulator, but you're right that there's no fabricated chip. I'm open to whatever fits best — a new FPGA category, the software list, or staying in hardware with a clear "FPGA implementation" label. Happy to restructure the entry to match whatever you decide.

On the publications: they're preprints on Zenodo, not peer-reviewed. I've updated the listing to make that clear.

On disclosure: I'm Henry Shulayev Barnes, founder of Catalyst Neuromorphic and a student at the University of Aberdeen. I should have stated that upfront, apologies.

I've pushed an update that also fixes several errors in the original submission: corrected the licensing to Apache 2.0 (was incorrectly listed as BSL 1.1), added N3, updated benchmark numbers, removed the cloud API references, and trimmed the entry to match the density of the other hardware listings.

[Nelias]

@aMarcireau there are already Verilog and VHDL entries in hardware as they are literally "Hardware Description Language" but obviously fully digital: ODIN, ReckOn, TEXEL, SENNECA, probably Syntzulu in the future so I think N1 fits here without a problem.

I will check now what those are doing and review the insert if there is a possibility of training them or accelerating available SNNs.

[Nelias]

@Mr-wabbit Did you use AI to write that FPGA code? If so you can not grant it any license. You do not have any prior experience with computer engineering based on your LinkedIn so it is unlikely that you learned it on your own but I might be wrong if that is your hobby or passion for years. Do include some other projects that you did in the past when it comes to chip design or digital computing in general, maybe some embedded open hardware or software if you have those.

@aMarcireau I think it is an okay HDL code but it should be marked as public domain license if it was generated with AI. In general this addition would require an opinion from at least 5 ONM members or more. @Jegp?

IMPORTANT! Zenodo papers are no longer possible to read and there is 403 error so the stuff was removed or closed.

[Nelias]

@aMarcireau the association with Aberdeen University is confirmed here: https://www.abdn.ac.uk/news/25605/

The company is truly registered in the UK: https://find-and-update.company-information.service.gov.uk/officers/IjTK8FUjrMVFNB9b17mkEihFbI0/appointments

I still think the code itself might be LLM generated as the GitHub account has no entries in 2023, 2024, 2025 only in 2026 when the company was founded in February 2026 so it would take just 3 months to develop new NMC chips, which I as an FPGA Developer judge as impossible to do so alone.

I did see a lot of scam while running Neuromorphicism and even I was the target of such false NMC stuff so I am very very cautious when it comes to this topic. My opinion is to hold this contribution for 1 year and maybe then it will be proven worthy or faithful.

CORRECTION: I found the papers on the company website but they are still missing in Zenodo.

[Mr-wabbit]

Hi, thanks for taking a look into the public records @Nelias , my public history is short as the organisation was created at the same time as the company back in February. For additional verifiable anchors beyond Companies House: the underlying architectures are filed as UK patent applications in my name and assigned to Catalyst Neuromorphic Ltd (searchable on the UK IPO database). As for the Zenodo issue I cannot replicate this issue on my end, the DOI links are all working just fine on my end. However there was a Zenodo incident recently this month maybe it may have something to do with this? On the broader question of evaluating the contribution, I'm not going to fight your proposal to hold it for review, your reasoning is quite fair and I completely understand given your prior experience. I would rather earn the inclusion over time than try to push for something the community isn't comfortable with, in the mean time I'll keep publishing new benchmarks, RTL, papers, etc. and potentially this may be revisited in the future. Thank you for your time.

[Nelias]

@Mr-wabbit would be good to see a video of it working on FPGA this could convince others. I could compile it or evaluate it but right now I don't have the time for such free work. Maybe other FPGA Devs will do it but there are not many in Neuromorphic Computing community.

So you worked on this stuff for years before 2026?

[Mr-wabbit]

Hi, on the video will do, I'll record SHD running on N1 on the F2 box, with the spike output and the terminal both on screen. I'm heavily preoccupied with other work at the moment so aiming for the next few weeks, if that works for you. As for the timeline, while my company has only been around since February, my interest in the field is much older, going back a few years. I deliberately kept the work private until I was ready to publish.