Enforce x0 Register Write Protection in Decoder with Verification Testbench

[Anubhav-30]

This PR ensures compliance with RISC-V specification by preventing writes to the x0 register.

• Updated write enable logic to block writes when destination register is x0
• Maintains existing illegal instruction protections
• Added System Verilog testbench to verify behavior

This improves architectural correctness and prevents silent data corruption.

[azure-pipelines]

Azure Pipelines:
1 pipeline(s) were filtered out due to trigger conditions.

[SamuelRiedel]

We are closing this PR as the proposed changes do not align with our current development priorities, address any tracked issues, or meet our required technical standards.