Skip to content

decoder: Add formal-style safety assertions for control, memory, and illegal instruction handling #2387

New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Closed
Anubhav-30 wants to merge 1 commit into from
+29 −0
Closed

decoder: Add formal-style safety assertions for control, memory, and illegal instruction handling #2387

Changes from all commits
Commits
Show all changes
1 commit
Select commit
File filter

Filter by extension

Filter by extension
Conversations
Failed to load comments.
Loading
Jump to
Jump to file
Failed to load files.
Loading
Diff view
Diff view
29 changes: 29 additions & 0 deletions rtl/ibex_decoder.sv
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -1206,6 +1206,35 @@ module ibex_decoder #(
// Assertions //
////////////////

// 1. No register write on illegal instruction
`ASSERT(NoWriteOnIllegal,
illegal_insn_o |-> !rf_we_o
)

// 2. No memory request on illegal instruction
`ASSERT(NoMemReqOnIllegal,
illegal_insn_o |-> !data_req_o
)

// 3. No branch + jump at same time
`ASSERT(NoBranchAndJump,
!(branch_in_dec_o && jump_in_dec_o)
)

// 4. No CSR access on illegal instruction
`ASSERT(NoCSRAccessOnIllegal,
illegal_insn_o |-> !csr_access_o
)

// 5. Branch should not trigger memory
`ASSERT(NoMemDuringBranch,
branch_in_dec_o |-> !data_req_o
)
// 6. No register read on illegal instruction
`ASSERT(NoRFReadOnIllegal,
illegal_insn_o |-> !(rf_ren_a_o || rf_ren_b_o)
)

// Selectors must be known/valid.
`ASSERT(IbexRegImmAluOpKnown, (opcode == OPCODE_OP_IMM) |->
!$isunknown(instr[14:12]))
Expand Down