decoder: Strengthen illegal instruction containment and add verification testbench#2385
Closed
Anubhav-30 wants to merge 1 commit intolowRISC:masterfrom
Closed
decoder: Strengthen illegal instruction containment and add verification testbench#2385Anubhav-30 wants to merge 1 commit intolowRISC:masterfrom
Anubhav-30 wants to merge 1 commit intolowRISC:masterfrom
Conversation
Contributor
|
Duplicate of #2384 |
This file contains hidden or bidirectional Unicode text that may be interpreted or compiled differently than what appears below. To review, open the file in an editor that reveals hidden Unicode characters.
Learn more about bidirectional Unicode characters
Sign up for free
to join this conversation on GitHub.
Already have an account?
Sign in to comment
2 participants
Add this suggestion to a batch that can be applied as a single commit.This suggestion is invalid because no changes were made to the code.Suggestions cannot be applied while the pull request is closed.Suggestions cannot be applied while viewing a subset of changes.Only one suggestion per line can be applied in a batch.Add this suggestion to a batch that can be applied as a single commit.Applying suggestions on deleted lines is not supported.You must change the existing code in this line in order to create a valid suggestion.Outdated suggestions cannot be applied.This suggestion has been applied or marked resolved.Suggestions cannot be applied from pending reviews.Suggestions cannot be applied on multi-line comments.Suggestions cannot be applied while the pull request is queued to merge.Suggestion cannot be applied right now. Please check back later.
This PR enhances illegal instruction handling in the decoder by ensuring
all side-effect-causing signals are safely disabled, including memory
control signals.
Additionally, a dedicated testbench is added to verify correct behavior
when illegal instructions are encountered.
The test injects an illegal instruction and confirms that no register
writes, memory requests, or control flow changes are triggered.
This improves robustness and aligns behavior with real hardware safety expectations.