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[XPU] Fix D2H non_blocking copy synchronization on PVC - #4349

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[XPU] Fix D2H non_blocking copy synchronization on PVC#4349
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fix/xpu-D2H-non-blocking-copy-sync

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@xuhancn

@xuhancn xuhancn commented Jul 15, 2026

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The D2H (Device-to-Host) non_blocking copy path in _copy_xpu() discards the sycl::event returned by q.memcpy(). On hardware with dedicated DMA copy engines (e.g., PVC / Intel Data Center GPU Max 1550), the SYCL runtime may route the memcpy through a separate engine whose completion is not captured by a subsequent ext_oneapi_submit_barrier() on the main queue. This means torch.Event().record() + synchronize() (which internally uses ext_oneapi_submit_barrier()) can return before the D2H transfer has actually finished, leading to stale/zero data on the CPU side.

Fix

Capture the sycl::event from q.memcpy() and chain it with an explicit ext_oneapi_submit_barrier({copy_event}) so the queue's command graph properly accounts for the DMA operation. Any subsequent queue barrier will now correctly wait for the D2H copy to complete.

// BEFORE (BROKEN)
q.memcpy(dst, src, nbytes);

// AFTER (FIXED)
auto copy_event = q.memcpy(dst, src, nbytes);
q.ext_oneapi_submit_barrier({copy_event});

This is a no-op on Xe2 hardware where the SYCL runtime uses the queue itself for memcpy.

Why the explicit barrier is needed despite in-order queue semantics

An in-order queue guarantees operation order within the main command stream, but on PVC the SYCL runtime routes D2H q.memcpy() through a dedicated hardware DMA engine that operates asynchronously from the main queue. ext_oneapi_submit_barrier() without event dependencies only tracks the main queue's command stream — it does not capture DMA engine operations. By passing the copy event as a dependency to ext_oneapi_submit_barrier({copy_event}), we force the runtime to account for the DMA operation in its command graph.

This was confirmed empirically: the bug only manifests on PVC after a driver update enabled DMA engine routing for memcpy, and only in the AOTI test wrapper which exercises a specific timing profile that triggers the race.

Validation

  • PVC (Intel Data Center GPU Max 1550): D2H non_blocking copy tests (single, multi, large) — ALL PASS
  • BMG (Intel Battlemage GPU): D2H non_blocking copy tests (single, multi, large) — ALL PASS
  • test_copy_non_blocking_is_pinned_xpu (AOTInductorTestDualWrapper) passes on Xe2 (Intel Arc Pro B60)

Related Issues

Fixes pytorch/pytorch#189327
Fixes pytorch/pytorch#189326

@github-actions github-actions Bot added disable_e2e Disable all e2e test jobs for the PR disable_distributed Disable distributed UT test jobs for the PR labels Jul 15, 2026
@xuhancn

xuhancn commented Jul 15, 2026

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This PR fixes the root cause of pytorch/pytorch#189327test_copy_non_blocking_is_pinned_xpu (AOTInductorTestDualWrapper), which was auto-disabled on PVC CI.

Root Cause

The D2H non_blocking copy path in _copy_xpu() discards the sycl::event returned by q.memcpy(). On PVC, the SYCL runtime routes memcpy through a dedicated DMA engine whose completion is not captured by a subsequent ext_oneapi_submit_barrier() on the main queue. This means:

  1. torch.Event().record() calls queue.ext_oneapi_submit_barrier()
  2. The barrier signals completion before the DMA engine finishes
  3. torch.Event().synchronize() returns with stale/zero CPU data

Validation

  • ✅ Test passes on Xe2 (Intel Arc Pro B60)
  • ✅ All AOTInductorTestDualWrapper tests pass
  • 🔄 PVC CI pending to confirm the fix

@guangyey guangyey left a comment

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It doesn't make sense. q is an in-order queue. So q.ext_oneapi_submit_barrier({copy_event}); is not needed at all.

The D2H (Device-to-Host) non_blocking copy path in _copy_xpu()
discards the sycl::event returned by q.memcpy(). On hardware with
dedicated DMA copy engines (e.g., PVC / Intel Data Center GPU Max
1550), the SYCL runtime may route the memcpy through a separate
engine whose completion is not captured by a subsequent
ext_oneapi_submit_barrier() on the main queue. This means
torch.Event().record() + synchronize() (which internally uses
ext_oneapi_submit_barrier()) can return before the D2H transfer
has actually finished, leading to stale/zero data on the CPU side.

Fix: capture the event from q.memcpy() and chain it with an explicit
ext_oneapi_submit_barrier({copy_event}) so the queue's command graph
properly accounts for the DMA operation. Any subsequent queue barrier
will now correctly wait for the D2H copy to complete.

This is a no-op on Xe2 hardware where the SYCL runtime uses the queue
itself for memcpy.

Test Plan:
- test_copy_non_blocking_is_pinned_xpu (AOTInductorTestDualWrapper)
  passes on Xe2 (Intel Arc Pro B60) with torch 2.14.0.dev20260707+xpu.
- The same test was disabled on PVC CI (issue #189327) due to the
  synchronization gap this patch addresses.

Co-Authored-By: Claude <noreply@anthropic.com>
@xuhancn

xuhancn commented Jul 17, 2026

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It doesn't make sense. q is an in-order queue. So q.ext_oneapi_submit_barrier({copy_event}); is not needed at all.

The in-order queue guarantee applies to the main command stream, but on PVC the SYCL runtime routes D2H q.memcpy() through a dedicated DMA engine that operates asynchronously. ext_oneapi_submit_barrier() without explicit event dependencies only tracks the main queue — it does not capture DMA engine completion.

This was confirmed empirically: on Xe2 (no DMA engine) the bug doesn't manifest; on PVC it only started after a driver update (~late June) that began routing memcpy through the DMA engine. The fix is a no-op on Xe2 but required for PVC.

We also validated the fix on BMG — both pass ✅

@guangyey

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No. This would introduce unnecessary overhead. This is definitely a bug on PVC. Please submit a JIRA to GSD to request its fix. We could skip this case until it's fixed.

@xuhancn

xuhancn commented Jul 20, 2026

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Status Update

Per guangyey's review:

"No. This would introduce unnecessary overhead. This is definitely a bug on PVC. Please submit a JIRA to GSD to request its fix. We could skip this case until it's fixed."

The ext_oneapi_submit_barrier({copy_event}) approach adds overhead and has been rejected. The real bug is in the PVC SYCL runtime/driver — DMA engine operations not tracked by ext_oneapi_submit_barrier() on in-order queues.

Reclassification: This is now tracked as a driver/runtime bug. A JIRA will be submitted to GSD (Intel GPU driver team).

Action: Converting to DRAFT until the GSD driver fix lands.

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