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In this tutorial, you will create a simple Simulink design using both standard Xilinx system generator blockset, as well as library blocks specific to CASPER boards (so-called "Yellow Blocks"). At the end of this tutorial, you will know how to generate an fpg file, program it to a CASPER FPGA board, and interact with your running hardware design using casperfpga via a Python Interface.
Setup
The lab at the workshop is pre-configured with the CASPER libraries, MATLAB and Xilinx tools. See [1] for information about the local set up.