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1. cepdnaclk/e16-4yp-neuromorphic-architecture cepdnaclk/e16-4yp-neuromorphic-architecture Public

   Neuromorphic architectures are hardware architectures that use the biologically inspired neural functions as the basis of operation. Information processing based on spiking neuron architectures hav…

   VHDL 10 4

2. cepdnaclk/e16-co502-RV32IM-pipeline-implementation-group1 cepdnaclk/e16-co502-RV32IM-pipeline-implementation-group1 Public

   The objective of this project was to design and implement a 5 stage pipeline CPU to support the RISC-V instruction architecture. This pipeline CPU supports the entire RV32IM ISA which contains 45 i…

   Verilog 29 4

3. e16-co502-RV32IM-pipeline-implementation-group1 e16-co502-RV32IM-pipeline-implementation-group1 Public

   Forked from cepdnaclk/e16-co502-RV32IM-pipeline-implementation-group1

   This project is a pipeline implementation of RV32IM using verilog.

   Verilog

4. e16-3yp-waiterbot-system e16-3yp-waiterbot-system Public

   Forked from cepdnaclk/e16-3yp-waiterbot-system

   WaiterBot System - A system of interactive robots to deliver the orders in a restaurant.

5. mystore-api mystore-api Public

   JavaScript

6. single-cycle-cpu single-cycle-cpu Public

   Verilog