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DRAFT: Let stream-dse choose fused groups, placement and tiles for generated operators - #227

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asyms wants to merge 21 commits into

amd:develfrom

KULeuven-MICAS:iron/stream-dse

Commits on Oct 5, 2026
- Fold a runlist of one design into a single xclbin dispatch
  asyms
  committed
  b2e9e6e
- Hand stream-dse the kernel library as a KernelLibrary
  asyms
  committed
  3587b2b
- Share the stream-dse operator plumbing between operators
  asyms
  committed
  9b44148
- Add a stream-dse backed MHA prefill operator
  asyms
  committed
  6d68a4d
- Record stream's per-group port activity beside each generated design
  asyms
  committed
  5baab7f
- Let the generated operators pin their query or GEMM block
  asyms
  committed
  17076b6
- Trace the tiles and memory-tile DMA ports asked for
  asyms
  committed
  3ce4c97
- Record stream's estimate beside each generated design
  asyms
  committed
  dff2531
- Check stream's estimates against the NPU
  asyms
  committed
  4c5e2ab
- Key generated designs on stream's hardware descriptions too
  asyms
  committed
  6729f7a
- Build SiLU and mul at their call size and price each call as its core runs it
  asyms
  committed
  43d8ab1
- Export attention's heads as the leading axis of one workload
  asyms
  committed
  fe6c1fa
- Drop the iterated runtime sequence a design over every run makes redundant
  asyms
  committed
  7eed603
- Test the SwiGLU prefill where its hidden row is split across cores
  asyms
  committed
  5aba389
- Key stream designs on the solver backend and tidy the stream-dse operators
  asyms
  committed
  ef21b0c
- Read stream's activity rows by resource
  asyms
  committed
  5ebbd6b
- Use stream-dse 1.15.1 and dispatch a one-design sequence as its own xclbin
  asyms
  committed
  2466950
- Drop the single-xclbin dispatch
  asyms
  committed
  436c564
- Build stream kernels from the bindings stream records
  asyms
  committed
  7f6ac09
- Select stream-dse's constraint families by name
  asyms
  committed
  c921dee
Commits on Oct 9, 2026
- Put the port report in place of stream-dse's own memory_ports family
  asyms
  committed
  4d82203

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DRAFT: Let stream-dse choose fused groups, placement and tiles for generated operators - #227

DRAFT: Let stream-dse choose fused groups, placement and tiles for generated operators#227
asyms wants to merge 21 commits into
amd:develfrom
KULeuven-MICAS:iron/stream-dse

Commits on Oct 5, 2026

Fold a runlist of one design into a single xclbin dispatch

Hand stream-dse the kernel library as a KernelLibrary

Share the stream-dse operator plumbing between operators

Add a stream-dse backed MHA prefill operator

Record stream's per-group port activity beside each generated design

Let the generated operators pin their query or GEMM block

Trace the tiles and memory-tile DMA ports asked for

Record stream's estimate beside each generated design

Check stream's estimates against the NPU

Key generated designs on stream's hardware descriptions too

Build SiLU and mul at their call size and price each call as its core runs it

Export attention's heads as the leading axis of one workload

Drop the iterated runtime sequence a design over every run makes redundant

Test the SwiGLU prefill where its hidden row is split across cores

Key stream designs on the solver backend and tidy the stream-dse operators

Read stream's activity rows by resource

Use stream-dse 1.15.1 and dispatch a one-design sequence as its own xclbin

Drop the single-xclbin dispatch

Build stream kernels from the bindings stream records

Select stream-dse's constraint families by name

Commits on Oct 9, 2026

Put the port report in place of stream-dse's own memory_ports family