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Add conditional expressions - #490

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Schottkyc137 merged 8 commits into
VHDL-LS:masterfrom
Schottkyc137:conditional-expressions
Jul 13, 2026
Merged

Add conditional expressions#490
Schottkyc137 merged 8 commits into
VHDL-LS:masterfrom
Schottkyc137:conditional-expressions

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@Schottkyc137 Schottkyc137 commented Jul 2, 2026

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Adds VHDL-2019 conditional expression. This enabled VHDL-LS to parse and analyse syntax like the following:

constant foo : std_logic := '1' when bar else '0';
attribute shreg_extract of my_srl : signal is "yes" when extract else "no";

@Schottkyc137 Schottkyc137 mentioned this pull request Jul 11, 2026
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Schottkyc137 force-pushed the conditional-expressions branch from 4591430 to 539f49f Compare July 12, 2026 00:59
@Schottkyc137
Schottkyc137 merged commit 2b4efeb into VHDL-LS:master Jul 13, 2026
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