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VHDL Syntax: Implement structural validation for VHDL syntax tree and fix several parser <-> YAML inconsistencies - #488

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Schottkyc137 merged 3 commits into
VHDL-LS:masterfrom
Schottkyc137:tree-validator
Aug 8, 2026
Merged

VHDL Syntax: Implement structural validation for VHDL syntax tree and fix several parser <-> YAML inconsistencies#488
Schottkyc137 merged 3 commits into
VHDL-LS:masterfrom
Schottkyc137:tree-validator

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The main contribution is a SyntaxNode::validate() function and associated machinery to verify a SyntaxNode. With that, many SyntaxNode <-> YAML inconsistencies are fixed.

This PR looks like a lot, but most changes come from the regenerated snapshot test.

@Schottkyc137
Schottkyc137 merged commit c7c3893 into VHDL-LS:master Aug 8, 2026
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