[davekeeshan]

Summary

Fixes #217.

A wbuffer_trigger that names a field (a singlepulse field) or a propref
(trig_vec->anded) is dereferenced by WriteBuffering.get_raw_trigger() to
field_storage.<path>.value. The module template emitted the write-buffer
implementation before the field storage struct, so the generated RTL read
field_storage before declaring it.

IEEE 1800 requires data to be declared before use, so strict tools reject the
output:

Tool	Before this change
Verilator 5.x	accepts
Icarus Verilog	Unable to bind wire/reg/memory 'field_storage'
xezim	Undefined variable 'field_storage': referenced before its declaration

Change

src/peakrdl_regblock/module_tmpl.sv: emit field_logic.get_storage_struct()
ahead of the write-buffer section when the design has buffered write registers.
The field storage struct does not depend on write buffering, so the field logic
section keeps the declaration for designs without them.

Designs without buffered write registers render byte-identically (verified by
diffing the tests/test_basic output before and after).

Test

tests/test_write_buffer/test_declaration_order.py exports
tests/test_write_buffer/regblock.rdl with the passthrough CPUIF and asserts
that field_storage_t field_storage; precedes its first read. That RDL already
covers both trigger forms, so no RDL change is needed. The test needs no
simulator and runs under --sim-tool skip.

Verified:

• fails on ed07496 (declaration at offset 26615, first use at offset 18829)
• passes with this change
• tests/test_write_buffer still passes on Verilator and on xezim

python -m pytest tests/test_write_buffer/test_declaration_order.py -q --sim-tool skip