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Fix wide fixedpoint readback #211

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Fix wide fixedpoint readback #211

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3a05445
adjust slice indices for wide fixedpoint readback
darsor Jul 29, 2026
b2fc080
add wide fixedpoint field regression test
darsor Aug 10, 2026
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7 changes: 7 additions & 0 deletions src/peakrdl_regblock/readback/readback_mux_generator.py
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Original file line number Diff line number Diff line change
Expand Up @@ -267,6 +267,13 @@ def get_wide_reg_subword_assignments(self, node: RegNode, fields: Sequence[Field
f_low -= field.low
f_high -= field.low

# Adjust for fixedpoint LSB (only for HWIF inputs)
if not field.implements_storage and self.exp.hwif.has_value_input(field):
fracwidth = field.get_property("fracwidth")
lsb = 0 if fracwidth is None else -fracwidth
f_low += lsb
f_high += lsb

if field.msb < field.lsb:
# Field gets bitswapped since it is in [low:high] orientation
# Mirror the low/high indexes
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13 changes: 13 additions & 0 deletions tests/test_wide_regs/regblock.rdl
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Expand Up @@ -108,4 +108,17 @@ addrmap top {

field {} f1[0:31] = 0x1234_5678;
} r_reg4;

// https://github.com/SystemRDL/PeakRDL-regblock/issues/210
reg {
regwidth = 32;
accesswidth = 16;
default hw=w;
default sw=r;

field {
intwidth = 16;
fracwidth = 16;
} f1[32];
} r_reg5;
};
6 changes: 6 additions & 0 deletions tests/test_wide_regs/tb_template.sv
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Expand Up @@ -118,4 +118,10 @@
cpuif.assert_read('h3A, 16'h1E6A);
assert(cb.hwif_out.r_reg4.f1.value == 32'h12345678);

// r_reg5
// https://github.com/SystemRDL/PeakRDL-regblock/issues/210
cb.hwif_in.r_reg5.f1.next <= 32'h8765_4321;
cpuif.assert_read('h3C, 16'h4321);
cpuif.assert_read('h3E, 16'h8765);

{% endblock %}
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