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fix width mismatch in counter overflow calculation (#197) - #198
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amykyta3
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Mar 20, 2026
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Looks good! Technically not an error since SystemVerilog is very clear about how it handles width expansion in the LRM, but its an easy enough change to get Verilator to stop complaining that i'm ok with it! Thanks! |
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Description of change
This fixes a Verilator error when generating counter registers. I have not run the unit test suite due to not being able to install Questa locally, but VCS and Verilator simulate correctly.
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