| 🔭 Working on | 🌱 Exploring |
|---|---|
| Design & Verification @ IP & SoC level | Advanced UVM methodologies & Formal Verification |
◉ Designing digital logic and verifying every corner case
◉ Turning waveforms into insights
◉ Finding bugs before they become silicon
◉ Ask me about Verilog, SystemVerilog, and FPGA-based system design
Usually one simulation away from either a breakthrough — or a brand new bug.

