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ShivamKurekar/README.md

Shivam Kurekar

RTL Design • FPGA Development • Verification


Currently

🔭 Working on 🌱 Exploring
Design & Verification @ IP & SoC level Advanced UVM methodologies & Formal Verification

What I do

◉  Designing digital logic and verifying every corner case

◉  Turning waveforms into insights

◉  Finding bugs before they become silicon

◉  Ask me about Verilog, SystemVerilog, and FPGA-based system design


My Tech Stack

📊 GitHub Activity

Usually one simulation away from either a breakthrough — or a brand new bug.

Pinned Loading

  1. D2L D2L Public

    Dual Data Link code in Verilog

    Verilog

  2. FIFO FIFO Public

    Synchronous and Asynchronous FIFO Designs

    Verilog

  3. hdmi_tang60k hdmi_tang60k Public

    HDMI/DVI with TANG MEGA NEO 60k

    Verilog

  4. MIPS32 MIPS32 Public

    A MIPS32 processor

    Verilog

  5. fifo_verification fifo_verification Public

    fifo verification using uvm

    SystemVerilog

  6. verification verification Public

    verification examples

    SystemVerilog