FAIL [ 0.506s] ( 820/1417) wgpu-test::wgpu-gpu [Executed] [Dx12/Microsoft Basic Render Driver/0] wgpu_gpu::shader::struct_layout::immediates_input_f16
stdout ───
running 1 test
test [Executed] [Dx12/Microsoft Basic Render Driver/0] wgpu_gpu::shader::struct_layout::immediates_input_f16 ... FAILED
failures:
---- [Executed] [Dx12/Microsoft Basic Render Driver/0] wgpu_gpu::shader::struct_layout::immediates_input_f16 ----
test panicked: tests\tests\wgpu-gpu\shader\struct_layout.rs:845:53: test "wgpu_gpu::shader::struct_layout::immediates_input_f16" did not behave as expected
failures:
[Executed] [Dx12/Microsoft Basic Render Driver/0] wgpu_gpu::shader::struct_layout::immediates_input_f16
test result: FAILED. 0 passed; 1 failed; 0 ignored; 0 measured; 713 filtered out; finished in 0.46s
stderr ───
[2026-08-15T08:59:03Z DEBUG wgpu_hal::dx12::device_creation] Using D3D12 Agility SDK v619 from 'D:\a\wgpu\wgpu\xtask/..\target/agility-sdk\build/native/bin/x64'
[2026-08-15T08:59:03Z DEBUG wgpu_hal::dx12::instance] Using dynamic DXC for shader compilation
[2026-08-15T08:59:03Z DEBUG wgpu_core::instance] Instance::new: created Dx12 backend
[2026-08-15T08:59:03Z INFO wgpu_core::instance] Instance::enumerate_adapters
[2026-08-15T08:59:03Z INFO wgpu_core::instance] Adapter AdapterInfo { name: "Microsoft Basic Render Driver", vendor: 5140, device: 140, device_type: Cpu, device_pci_bus_id: "", driver: "1.0.20.0", driver_info: "", backend: Dx12, subgroup_min_size: 4, subgroup_max_size: 128, transient_saves_memory: Some(false), limit_bucket: None }
[2026-08-15T08:59:03Z INFO wgpu_test::init] Testing using adapter: AdapterInfo {
name: "Microsoft Basic Render Driver",
vendor: 5140,
device: 140,
device_type: Cpu,
device_pci_bus_id: "",
driver: "1.0.20.0",
driver_info: "",
backend: Dx12,
subgroup_min_size: 4,
subgroup_max_size: 128,
transient_saves_memory: Some(
false,
),
limit_bucket: None,
}
[2026-08-15T08:59:03Z INFO wgpu_test::run] TEST: wgpu_gpu::shader::struct_layout::immediates_input_f16
[2026-08-15T08:59:03Z INFO wgpu_core::instance] Adapter::request_device
[2026-08-15T08:59:03Z INFO wgpu_core::instance] Adapter::create_device_and_queue_from_hal
[2026-08-15T08:59:03Z DEBUG wgpu_hal::dx12::device] Naga generated shader for "main" at Compute:
struct __dynamic_buffer_offsetsTy1 {
uint _0;
};
ConstantBuffer<__dynamic_buffer_offsetsTy1> __dynamic_buffer_offsets1: register(b1, space1);
struct OffsetPc {
uint inner;
};
RWByteAddressBuffer dst_ : register(u0);
ByteAddressBuffer src : register(t0);
ConstantBuffer<OffsetPc> offset: register(b0);
typedef uint ret_Constructarray6_uint_[6];
ret_Constructarray6_uint_ Constructarray6_uint_(uint arg0, uint arg1, uint arg2, uint arg3, uint arg4, uint arg5) {
uint ret[6] = { arg0, arg1, arg2, arg3, arg4, arg5 };
return ret;
}
[numthreads(1, 1, 1)]
void main()
{
bool local = (bool)0;
bool local_1 = (bool)0;
uint _e3 = offset.inner;
uint _e5 = asuint(src.Load(_e3*4+__dynamic_buffer_offsets1._0));
uint _e9 = offset.inner;
uint _e13 = asuint(src.Load((_e9 + 1u)*4+__dynamic_buffer_offsets1._0));
uint _e17 = offset.inner;
uint _e21 = asuint(src.Load((_e17 + 2u)*4+__dynamic_buffer_offsets1._0));
uint3 src_1 = uint3(_e5, _e13, _e21);
if (!((src_1.x > 65535u))) {
local = (src_1.y > 65535u);
} else {
local = true;
}
bool _e32 = local;
if (!(_e32)) {
local_1 = (src_1.z > 65535u);
} else {
local_1 = true;
}
bool _e39 = local_1;
if (_e39) {
{
uint _value3[6] = Constructarray6_uint_(0u, 0u, 0u, 0u, 0u, 0u);
dst_.Store(0, asuint(_value3[0]));
dst_.Store(4, asuint(_value3[1]));
dst_.Store(8, asuint(_value3[2]));
dst_.Store(12, asuint(_value3[3]));
dst_.Store(16, asuint(_value3[4]));
dst_.Store(20, asuint(_value3[5]));
}
return;
} else {
{
uint _value3[6] = Constructarray6_uint_(src_1.x, src_1.y, src_1.z, src_1.x, src_1.y, src_1.z);
dst_.Store(0, asuint(_value3[0]));
dst_.Store(4, asuint(_value3[1]));
dst_.Store(8, asuint(_value3[2]));
dst_.Store(12, asuint(_value3[3]));
dst_.Store(16, asuint(_value3[4]));
dst_.Store(20, asuint(_value3[5]));
}
return;
}
}
[2026-08-15T08:59:03Z DEBUG wgpu_hal::dx12::device] Naga generated shader for "main" at Compute:
struct __dynamic_buffer_offsetsTy1 {
uint _0;
};
ConstantBuffer<__dynamic_buffer_offsetsTy1> __dynamic_buffer_offsets1: register(b1, space1);
struct MetadataEntry {
uint src_offset;
uint dst_offset;
uint vertex_or_index_limit;
uint instance_limit;
};
struct MetadataRange {
uint start;
uint count;
};
static const uint OFFSET_MASK = 1073741823u;
static const bool supports_indirect_first_instance = false;
static const bool write_d3d12_special_constants = true;
ConstantBuffer<MetadataRange> metadata_range: register(b0);
ByteAddressBuffer metadata : register(t0);
ByteAddressBuffer src : register(t1);
RWByteAddressBuffer dst_ : register(u0);
bool is_bit_set(uint data, uint index)
{
return (((data >> index) & 1u) == 1u);
}
MetadataEntry ConstructMetadataEntry(uint arg0, uint arg1, uint arg2, uint arg3) {
MetadataEntry ret = (MetadataEntry)0;
ret.src_offset = arg0;
ret.dst_offset = arg1;
ret.vertex_or_index_limit = arg2;
ret.instance_limit = arg3;
return ret;
}
[numthreads(64, 1, 1)]
void main(uint3 global_invocation_id : SV_DispatchThreadID)
{
bool failed = false;
bool local = (bool)0;
bool local_1 = (bool)0;
uint _e4 = metadata_range.count;
if ((global_invocation_id.x >= _e4)) {
return;
}
uint _e9 = metadata_range.start;
MetadataEntry metadata_1 = ConstructMetadataEntry(asuint(metadata.Load((_e9 + global_invocation_id.x)*16+0)), asuint(metadata.Load((_e9 + global_invocation_id.x)*16+4)), asuint(metadata.Load((_e9 + global_invocation_id.x)*16+8)), asuint(metadata.Load((_e9 + global_invocation_id.x)*16+12)));
const bool _e18 = is_bit_set(metadata_1.src_offset, 31u);
uint src_base_offset = (metadata_1.src_offset & OFFSET_MASK);
uint dst_base_offset = (metadata_1.dst_offset & OFFSET_MASK);
uint first_vertex_or_index = asuint(src.Load((src_base_offset + 2u)*4+__dynamic_buffer_offsets1._0));
uint vertex_or_index_count = asuint(src.Load((src_base_offset + 0u)*4+__dynamic_buffer_offsets1._0));
{
const bool _e37 = is_bit_set(metadata_1.dst_offset, 30u);
bool sub_overflows = (metadata_1.vertex_or_index_limit < first_vertex_or_index);
bool _e40 = failed;
if (sub_overflows) {
local = !(_e37);
} else {
local = false;
}
bool _e45 = local;
failed = (_e40 | _e45);
uint vertex_or_index_limit = (metadata_1.vertex_or_index_limit - first_vertex_or_index);
bool _e49 = failed;
failed = (_e49 | (vertex_or_index_limit < vertex_or_index_count));
}
uint first_instance = asuint(src.Load(((src_base_offset + 3u) + uint(_e18))*4+__dynamic_buffer_offsets1._0));
uint instance_count = asuint(src.Load((src_base_offset + 1u)*4+__dynamic_buffer_offsets1._0));
{
const bool _e66 = is_bit_set(metadata_1.dst_offset, 31u);
bool sub_overflows_1 = (metadata_1.instance_limit < first_instance);
bool _e69 = failed;
if (sub_overflows_1) {
local_1 = !(_e66);
} else {
local_1 = false;
}
bool _e74 = local_1;
failed = (_e69 | _e74);
uint instance_limit = (metadata_1.instance_limit - first_instance);
bool _e78 = failed;
failed = (_e78 | (instance_limit < instance_count));
}
if (true) {
bool _e84 = failed;
failed = (_e84 | (first_instance != 0u));
}
bool _e93 = failed;
if (_e93) {
if (write_d3d12_special_constants) {
dst_.Store((dst_base_offset + 0u)*4, asuint(0u));
dst_.Store((dst_base_offset + 1u)*4, asuint(0u));
dst_.Store((dst_base_offset + 2u)*4, asuint(0u));
}
dst_.Store(((dst_base_offset + 3u) + 0u)*4, asuint(0u));
dst_.Store(((dst_base_offset + 3u) + 1u)*4, asuint(0u));
dst_.Store(((dst_base_offset + 3u) + 2u)*4, asuint(0u));
dst_.Store(((dst_base_offset + 3u) + 3u)*4, asuint(0u));
if (_e18) {
dst_.Store(((dst_base_offset + 3u) + 4u)*4, asuint(0u));
return;
} else {
return;
}
} else {
if (write_d3d12_special_constants) {
uint _e151 = asuint(src.Load(((src_base_offset + 2u) + uint(_e18))*4+__dynamic_buffer_offsets1._0));
dst_.Store((dst_base_offset + 0u)*4, asuint(_e151));
uint _e162 = asuint(src.Load(((src_base_offset + 3u) + uint(_e18))*4+__dynamic_buffer_offsets1._0));
dst_.Store((dst_base_offset + 1u)*4, asuint(_e162));
dst_.Store((dst_base_offset + 2u)*4, asuint(0u));
}
uint _e177 = asuint(src.Load((src_base_offset + 0u)*4+__dynamic_buffer_offsets1._0));
dst_.Store(((dst_base_offset + 3u) + 0u)*4, asuint(_e177));
uint _e187 = asuint(src.Load((src_base_offset + 1u)*4+__dynamic_buffer_offsets1._0));
dst_.Store(((dst_base_offset + 3u) + 1u)*4, asuint(_e187));
uint _e197 = asuint(src.Load((src_base_offset + 2u)*4+__dynamic_buffer_offsets1._0));
dst_.Store(((dst_base_offset + 3u) + 2u)*4, asuint(_e197));
uint _e207 = asuint(src.Load((src_base_offset + 3u)*4+__dynamic_buffer_offsets1._0));
dst_.Store(((dst_base_offset + 3u) + 3u)*4, asuint(_e207));
if (_e18) {
uint _e217 = asuint(src.Load((src_base_offset + 4u)*4+__dynamic_buffer_offsets1._0));
dst_.Store(((dst_base_offset + 3u) + 4u)*4, asuint(_e217));
return;
} else {
return;
}
}
}
[2026-08-15T08:59:03Z INFO wgpu_core::instance] Created Device 0x211d2f569a0
[2026-08-15T08:59:03Z INFO wgpu_core::instance] Created Queue 0x211d2d31ec0
[2026-08-15T08:59:03Z INFO wgpu_core::device::resource] Device::create_bind_group_layout -> 0x211d2d38e50
[2026-08-15T08:59:03Z INFO wgpu_core::device::resource] Device::create_buffer("input buffer") -> 0x211d2d3abf0
[2026-08-15T08:59:03Z INFO wgpu_core::device::resource] Device::create_buffer("output buffer") -> 0x211d2d3a7d0
[2026-08-15T08:59:03Z INFO wgpu_core::device::resource] Device::create_buffer("mapping buffer") -> 0x211d2d3a250
[2026-08-15T08:59:03Z INFO wgpu_core::device::resource] Device::create_bind_group -> 0x211d2b41a20
[2026-08-15T08:59:03Z INFO wgpu_core::device::resource] Device::create_pipeline_layout -> 0x211d305f020
[2026-08-15T08:59:03Z INFO wgpu_core::device::resource] Device::create_shader_module -> 0x211d2d22500
[2026-08-15T08:59:03Z DEBUG wgpu_hal::dx12::device] Naga generated shader for "cs_main" at Compute:
struct NagaConstants {
int first_vertex;
int first_instance;
uint other;
};
ConstantBuffer<NagaConstants> _NagaConstants: register(b1, space1);
struct CustomStruct {
half scalar1_;
half scalar2_;
int _pad2_0;
half3 v3_;
half tuck_in;
half scalar4_;
uint larger;
};
ConstantBuffer<CustomStruct> input: register(b0);
RWByteAddressBuffer output : register(u0);
uint naga_extractBits(
uint e,
uint offset,
uint count
) {
uint w = 32;
uint o = min(offset, w);
uint c = min(count, w - o);
return (c == 0 ? 0 : (e << (w - c - o)) >> (w - c));
}
uint naga_f2u32(half value) {
return uint(clamp(value, 0.0h, 65504.0h));
}
[numthreads(1, 1, 1)]
void cs_main()
{
half _e4 = input.scalar1_;
output.Store(0, asuint(naga_f2u32(_e4)));
half _e10 = input.scalar2_;
output.Store(4, asuint(naga_f2u32(_e10)));
half _e17 = input.v3_.x;
output.Store(8, asuint(naga_f2u32(_e17)));
half _e24 = input.v3_.y;
output.Store(12, asuint(naga_f2u32(_e24)));
half _e31 = input.v3_.z;
output.Store(16, asuint(naga_f2u32(_e31)));
half _e37 = input.tuck_in;
output.Store(20, asuint(naga_f2u32(_e37)));
half _e43 = input.scalar4_;
output.Store(24, asuint(naga_f2u32(_e43)));
uint _e49 = input.larger;
output.Store(28, asuint(uint(naga_extractBits(_e49, 0u, 16u))));
uint _e58 = input.larger;
output.Store(32, asuint(uint(naga_extractBits(_e58, 16u, 16u))));
return;
}
[2026-08-15T08:59:03Z INFO wgpu_core::device::resource] Device::create_compute_pipeline -> 0x211d2b409e0
[2026-08-15T08:59:03Z INFO wgpu_core::device::queue] Queue::write_buffer
[2026-08-15T08:59:03Z INFO wgpu_core::device::resource] Device::create_command_encoder -> 0x211d2d8cbb0
[2026-08-15T08:59:03Z INFO wgpu_core::command::transfer] CommandEncoder::copy_buffer_to_buffer 0x211d2d3a7d0 -> 0x211d2d3a250 Some(128)bytes
[2026-08-15T08:59:03Z INFO wgpu_core::command] Begin encoding compute pass with 'cpass f16 alignment' label
[2026-08-15T08:59:03Z INFO wgpu_core::command::pass] Pass::set_bind_group 0 BindGroup with '' label
[2026-08-15T08:59:03Z INFO wgpu_core::command::compute] ComputePass::dispatch [1, 1, 1]
[2026-08-15T08:59:03Z INFO wgpu_core::command] Finished encoding compute pass (success)
[2026-08-15T08:59:03Z INFO wgpu_core::command] CommandEncoder::drop 0x211d2d8cbb0
[2026-08-15T08:59:03Z INFO wgpu_core::command] Drop CommandEncoder with '' label
[2026-08-15T08:59:03Z INFO wgpu_core::device::queue] Queue::submit
[2026-08-15T08:59:03Z INFO wgpu_core::device::queue] Queue::submit returned submit index 1
[2026-08-15T08:59:03Z INFO wgpu_core::command] CommandBuffer::drop 0x211d2d8cfd0
[2026-08-15T08:59:03Z INFO wgpu_core::command] Drop CommandBuffer with '' label
[2026-08-15T08:59:03Z INFO wgpu_core::resource] Buffer::map_async 0x211d2d3a250 offset 0 size Some(128) op: BufferMapOperation { host: Read, callback: Some("?") }
[2026-08-15T08:59:03Z INFO wgpu_core::device::resource] Device::poll Wait { submission_index: None, timeout: None }
[2026-08-15T08:59:03Z INFO wgpu_core::resource] Destroy raw StagingBuffer
[2026-08-15T08:59:03Z INFO wgpu_core::resource] Destroy raw StagingBuffer
[2026-08-15T08:59:03Z INFO wgpu_core::resource] Buffer::get_mapped_range 0x211d2d3a250 offset 0 size Some(128)
[2026-08-15T08:59:03Z INFO wgpu_core::resource] Buffer::unmap 0x211d2d3a250
[2026-08-15T08:59:03Z INFO wgpu_core::pipeline] ComputePipeline::drop 0x211d2b409e0
[2026-08-15T08:59:03Z INFO wgpu_core::pipeline] Destroy raw ComputePipeline with 'pipeline f16 alignment' label
[2026-08-15T08:59:03Z INFO wgpu_core::pipeline] ShaderModule::drop 0x211d2d22500
[2026-08-15T08:59:03Z INFO wgpu_core::pipeline] Destroy raw ShaderModule with 'shader f16 alignment' label
[2026-08-15T08:59:03Z INFO wgpu_core::device::resource] Device::create_shader_module -> 0x211d2b0eac0
[2026-08-15T08:59:03Z DEBUG wgpu_hal::dx12::device] Naga generated shader for "cs_main" at Compute:
struct NagaConstants {
int first_vertex;
int first_instance;
uint other;
};
ConstantBuffer<NagaConstants> _NagaConstants: register(b1, space1);
struct CustomStruct {
half2 m2__0; half2 m2__1;
row_major half3x3 m3_;
row_major half4x4 m4_;
};
ConstantBuffer<CustomStruct> input: register(b0);
RWByteAddressBuffer output : register(u0);
uint naga_f2u32(half value) {
return uint(clamp(value, 0.0h, 65504.0h));
}
half2x2 GetMatm2_OnCustomStruct(CustomStruct obj) {
return half2x2(obj.m2__0, obj.m2__1);
}
void SetMatm2_OnCustomStruct(CustomStruct obj, half2x2 mat) {
obj.m2__0 = mat[0];
obj.m2__1 = mat[1];
}
void SetMatVecm2_OnCustomStruct(CustomStruct obj, half2 vec, uint mat_idx) {
switch(mat_idx) {
case 0: { obj.m2__0 = vec; break; }
case 1: { obj.m2__1 = vec; break; }
}
}
void SetMatScalarm2_OnCustomStruct(CustomStruct obj, half scalar, uint mat_idx, uint vec_idx) {
switch(mat_idx) {
case 0: { obj.m2__0[vec_idx] = scalar; break; }
case 1: { obj.m2__1[vec_idx] = scalar; break; }
}
}
[numthreads(1, 1, 1)]
void cs_main()
{
half _e6 = GetMatm2_OnCustomStruct(input)[0].x;
output.Store(0, asuint(naga_f2u32(_e6)));
half _e14 = GetMatm2_OnCustomStruct(input)[0].y;
output.Store(4, asuint(naga_f2u32(_e14)));
half _e22 = GetMatm2_OnCustomStruct(input)[1].x;
output.Store(8, asuint(naga_f2u32(_e22)));
half _e30 = GetMatm2_OnCustomStruct(input)[1].y;
output.Store(12, asuint(naga_f2u32(_e30)));
half _e38 = input.m3_[0].x;
output.Store(16, asuint(naga_f2u32(_e38)));
half _e46 = input.m3_[0].y;
output.Store(20, asuint(naga_f2u32(_e46)));
half _e54 = input.m3_[0].z;
output.Store(24, asuint(naga_f2u32(_e54)));
half _e62 = input.m3_[1].x;
output.Store(28, asuint(naga_f2u32(_e62)));
half _e70 = input.m3_[1].y;
output.Store(32, asuint(naga_f2u32(_e70)));
half _e78 = input.m3_[1].z;
output.Store(36, asuint(naga_f2u32(_e78)));
half _e86 = input.m3_[2].x;
output.Store(40, asuint(naga_f2u32(_e86)));
half _e94 = input.m3_[2].y;
output.Store(44, asuint(naga_f2u32(_e94)));
half _e102 = input.m3_[2].z;
output.Store(48, asuint(naga_f2u32(_e102)));
half _e110 = input.m4_[0].x;
output.Store(52, asuint(naga_f2u32(_e110)));
half _e118 = input.m4_[0].y;
output.Store(56, asuint(naga_f2u32(_e118)));
half _e126 = input.m4_[0].z;
output.Store(60, asuint(naga_f2u32(_e126)));
half _e134 = input.m4_[0].w;
output.Store(64, asuint(naga_f2u32(_e134)));
half _e142 = input.m4_[1].x;
output.Store(68, asuint(naga_f2u32(_e142)));
half _e150 = input.m4_[1].y;
output.Store(72, asuint(naga_f2u32(_e150)));
half _e158 = input.m4_[1].z;
output.Store(76, asuint(naga_f2u32(_e158)));
half _e166 = input.m4_[1].w;
output.Store(80, asuint(naga_f2u32(_e166)));
half _e174 = input.m4_[2].x;
output.Store(84, asuint(naga_f2u32(_e174)));
half _e182 = input.m4_[2].y;
output.Store(88, asuint(naga_f2u32(_e182)));
half _e190 = input.m4_[2].z;
output.Store(92, asuint(naga_f2u32(_e190)));
half _e198 = input.m4_[2].w;
output.Store(96, asuint(naga_f2u32(_e198)));
half _e206 = input.m4_[3].x;
output.Store(100, asuint(naga_f2u32(_e206)));
half _e214 = input.m4_[3].y;
output.Store(104, asuint(naga_f2u32(_e214)));
half _e222 = input.m4_[3].z;
output.Store(108, asuint(naga_f2u32(_e222)));
half _e230 = input.m4_[3].w;
output.Store(112, asuint(naga_f2u32(_e230)));
return;
}
[2026-08-15T08:59:03Z INFO wgpu_core::device::resource] Device::create_compute_pipeline -> 0x211d2b41b60
[2026-08-15T08:59:03Z INFO wgpu_core::device::queue] Queue::write_buffer
[2026-08-15T08:59:03Z INFO wgpu_core::device::resource] Device::create_command_encoder -> 0x211d30b6a40
[2026-08-15T08:59:03Z INFO wgpu_core::command::transfer] CommandEncoder::copy_buffer_to_buffer 0x211d2d3a7d0 -> 0x211d2d3a250 Some(128)bytes
[2026-08-15T08:59:03Z INFO wgpu_core::command] Begin encoding compute pass with 'cpass f16 matrix alignment' label
[2026-08-15T08:59:03Z INFO wgpu_core::command::pass] Pass::set_bind_group 0 BindGroup with '' label
[2026-08-15T08:59:03Z INFO wgpu_core::command::compute] ComputePass::dispatch [1, 1, 1]
[2026-08-15T08:59:03Z INFO wgpu_core::command] Finished encoding compute pass (success)
[2026-08-15T08:59:03Z INFO wgpu_core::command] CommandEncoder::drop 0x211d30b6a40
[2026-08-15T08:59:03Z INFO wgpu_core::command] Drop CommandEncoder with '' label
[2026-08-15T08:59:03Z INFO wgpu_core::device::queue] Queue::submit
[2026-08-15T08:59:03Z INFO wgpu_core::device::queue] Queue::submit returned submit index 3
[2026-08-15T08:59:03Z INFO wgpu_core::command] CommandBuffer::drop 0x211d2bfba70
[2026-08-15T08:59:03Z INFO wgpu_core::command] Drop CommandBuffer with '' label
[2026-08-15T08:59:03Z INFO wgpu_core::resource] Buffer::map_async 0x211d2d3a250 offset 0 size Some(128) op: BufferMapOperation { host: Read, callback: Some("?") }
[2026-08-15T08:59:03Z INFO wgpu_core::device::resource] Device::poll Wait { submission_index: None, timeout: None }
[2026-08-15T08:59:03Z INFO wgpu_core::resource] Destroy raw StagingBuffer
[2026-08-15T08:59:03Z INFO wgpu_core::resource] Buffer::get_mapped_range 0x211d2d3a250 offset 0 size Some(128)
Inner test failure. Actual [0, 1, 2, 3, 8, 9, 10, 16, 17, 18, 24, 25, 26, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0]. Expected: [0, 1, 2, 3, 4, 5, 6, 8, 9, 10, 12, 13, 14, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31]. Test f16 matrix alignment
[2026-08-15T08:59:03Z INFO wgpu_core::resource] Buffer::unmap 0x211d2d3a250
[2026-08-15T08:59:03Z INFO wgpu_core::pipeline] ComputePipeline::drop 0x211d2b41b60
[2026-08-15T08:59:03Z INFO wgpu_core::pipeline] Destroy raw ComputePipeline with 'pipeline f16 matrix alignment' label
[2026-08-15T08:59:03Z INFO wgpu_core::pipeline] ShaderModule::drop 0x211d2b0eac0
[2026-08-15T08:59:03Z INFO wgpu_core::pipeline] Destroy raw ShaderModule with 'shader f16 matrix alignment' label
thread '<unnamed>' (5948) panicked at tests\tests\wgpu-gpu\shader\mod.rs:401:5:
Description
Uniform f16 matrix alignment test fails on dx12 and vulkan
Repro steps
Change this from
StoragetoUniform:wgpu/tests/tests/wgpu-gpu/shader/struct_layout.rs
Lines 756 to 769 in 6104009
Run
cargo nextest run --test wgpu-gpu struct_layoutExpected vs observed behavior
Expect the test to pass, but it fails.
On dx12:
The log on dx12
On Vulkan: