From 70b9725a04f9f98594e27cdae307f69bdbaba8ec Mon Sep 17 00:00:00 2001 From: Joseph Mattiello Date: Tue, 13 Oct 2026 15:28:34 -0400 Subject: [PATCH] sh4: make RTC R64CNT tick R64CNT is a free-running 7-bit counter incremented at 128 Hz (bit 0 is the 64 Hz bit, bit 6 the 1 Hz bit). It was registered read-only with no handler, so it always read 0. Code that waits for it to change, such as a BIOS boot delay loop, never exits. Derive it from the SH4 cycle count so it advances in emulated time, at the same rate as MAME's SH4 RTC. Co-Authored-By: Claude Opus 5.5 --- core/hw/sh4/modules/rtc.cpp | 10 +++++++++- 1 file changed, 9 insertions(+), 1 deletion(-) diff --git a/core/hw/sh4/modules/rtc.cpp b/core/hw/sh4/modules/rtc.cpp index b312927d79..1c885fcfe6 100644 --- a/core/hw/sh4/modules/rtc.cpp +++ b/core/hw/sh4/modules/rtc.cpp @@ -4,9 +4,17 @@ #include "hw/hwreg.h" #include "hw/sh4/sh4_mmr.h" #include "modules.h" +#include "hw/sh4/sh4_sched.h" RTCRegisters rtc; +// R64CNT is a free-running 7-bit counter incremented at 128 Hz: bit 0 is the +// 64 Hz bit and bit 6 the 1 Hz bit, so it wraps once per second. +static u8 read_R64CNT(u32 addr) +{ + return (u8)((sh4_sched_now64() / (SH4_MAIN_CLOCK / 128)) & 0x7F); +} + void RTCRegisters::init() { super::init(); @@ -14,7 +22,7 @@ void RTCRegisters::init() // NAOMI reads from at least RTC_R64CNT //RTC R64CNT 0xFFC80000 0x1FC80000 8 Held Held Held Held Pclk - setReadOnly(); + setReadOnly(read_R64CNT); //RTC RSECCNT H'FFC8 0004 H'1FC8 0004 8 Held Held Held Held Pclk setRW();