From 3a05445fd5d8a0a9ce7b8814d47cb96b6156ae71 Mon Sep 17 00:00:00 2001 From: Dana Sorensen Date: Wed, 29 Jul 2026 10:32:31 -0600 Subject: [PATCH 1/2] adjust slice indices for wide fixedpoint readback --- src/peakrdl_regblock/readback/readback_mux_generator.py | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/src/peakrdl_regblock/readback/readback_mux_generator.py b/src/peakrdl_regblock/readback/readback_mux_generator.py index 34d78916..f5211ce8 100644 --- a/src/peakrdl_regblock/readback/readback_mux_generator.py +++ b/src/peakrdl_regblock/readback/readback_mux_generator.py @@ -267,6 +267,13 @@ def get_wide_reg_subword_assignments(self, node: RegNode, fields: Sequence[Field f_low -= field.low f_high -= field.low + # Adjust for fixedpoint LSB (only for HWIF inputs) + if not field.implements_storage and self.exp.hwif.has_value_input(field): + fracwidth = field.get_property("fracwidth") + lsb = 0 if fracwidth is None else -fracwidth + f_low += lsb + f_high += lsb + if field.msb < field.lsb: # Field gets bitswapped since it is in [low:high] orientation # Mirror the low/high indexes From b2fc080560b0e0f5a90baa555b1353966798d389 Mon Sep 17 00:00:00 2001 From: Dana Sorensen Date: Sun, 9 Aug 2026 21:24:29 -0600 Subject: [PATCH 2/2] add wide fixedpoint field regression test --- tests/test_wide_regs/regblock.rdl | 13 +++++++++++++ tests/test_wide_regs/tb_template.sv | 6 ++++++ 2 files changed, 19 insertions(+) diff --git a/tests/test_wide_regs/regblock.rdl b/tests/test_wide_regs/regblock.rdl index b3d4ca41..49504e1e 100644 --- a/tests/test_wide_regs/regblock.rdl +++ b/tests/test_wide_regs/regblock.rdl @@ -108,4 +108,17 @@ addrmap top { field {} f1[0:31] = 0x1234_5678; } r_reg4; + + // https://github.com/SystemRDL/PeakRDL-regblock/issues/210 + reg { + regwidth = 32; + accesswidth = 16; + default hw=w; + default sw=r; + + field { + intwidth = 16; + fracwidth = 16; + } f1[32]; + } r_reg5; }; diff --git a/tests/test_wide_regs/tb_template.sv b/tests/test_wide_regs/tb_template.sv index 8c261c6e..3a2dada5 100644 --- a/tests/test_wide_regs/tb_template.sv +++ b/tests/test_wide_regs/tb_template.sv @@ -118,4 +118,10 @@ cpuif.assert_read('h3A, 16'h1E6A); assert(cb.hwif_out.r_reg4.f1.value == 32'h12345678); + // r_reg5 + // https://github.com/SystemRDL/PeakRDL-regblock/issues/210 + cb.hwif_in.r_reg5.f1.next <= 32'h8765_4321; + cpuif.assert_read('h3C, 16'h4321); + cpuif.assert_read('h3E, 16'h8765); + {% endblock %}