Question of the composition of flit

[Alexander-0619]

Hi!!!

I carefully reviewed the vnet_router code and have some questions:

1.In the packet transmission design, is there no explicit labeling of head/body/tail for each flit? I've seen some NoCs define flit types this way; with flit type data, other nodes can identify which flits belong to a complete packet.

**Head Flit**
Max_width+2b---------------------------------------------0
| FLIT_TYPE (2b) | X_DEST | Y_DEST | X_SRC | Y_SRC | PKT_WIDTH | MESSAGE |
+--------------------------------------------------------+

**Body/Tail Flit**
Max_width+2b---------------------------------------------0
| FLIT_TYPE (2b)  |   MESSAGE                                            |
+--------------------------------------------------------+

2.Additionally, each flit carries tgt_id and src_id, but for flits within the same packet, the src_id and tgt_id is identical. Is this necessary?(Is this design related to whether different channels in the flit of the CHI protocol all contain tgt id and src id)

[Aquaticfuller]

Hello @Alexander-0619

1. This design is based on the CHI protocol. In that protocol, each flit has its own header, as I believe in Arm's consumption. This protocol and related NoC IPs are designed for recent technology nodes with abundant routing resources, allowing each channel width can be wide enough to carry a complete message rather than cut them into multiple flits. This also applies to their decision between multiple physical channels vs. virtual channel, basically they choose physical channels for better bandwidth. In our NoC design, we also adhere to their assumptions.
2. Continue the previous discussion, so in the CHI case, basically only the packages on the data channel can be segmented into multiple flits. But in CHI design, even each data flit equips a full header, including the id you mentioned. This is, of course, an overhead on the channel wiring, but also simplifies the NoC router design as well as adaptive routing. Again, Arm observe that today there is an abundant wiring resource on chip.